View IS61VPS102436A_4537903.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IS61VPS102436A IS61LPS102436A IS61VPS204818A IS61LPS204818A 1Mb x 36, 2Mb x 18 36Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
FEATURES
* Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * Burst sequence control using MODE input * Three chip enable option for simple depth expansion and address pipelining * Common data inputs and data outputs * Auto Power-down during deselect * Single cycle deselect * Snooze MODE for reduced-power standby * Power Supply LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5% * JEDEC 100-Pin TQFP and 165-ball PBGA packages * Lead-free available
MARCH 2008
DESCRIPTION The ISSI IS61LPS/VPS102436A and IS61LPS/VPS
204818A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS/VPS102436A is organized as 1,048,476 words by 36 bits. The IS61LPS/VPS204818A is organized as 2M-word by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positiveedge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency 200 3.1 5 200 166 3.5 6 166 Units ns ns MHz
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
1
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
BLOCK DIAGRAM
MODE Q0 A0'
CLK
CLK
A0
BINARY COUNTER
ADV ADSC ADSP CE CLR Q1 A1' A1
1Mx36; 2Mx18 MEMORY ARRAY
18/19 20/21
20/21 A D Q
ADDRESS REGISTER
CE CLK 36, or 18 36, or 18
GW BWE BW(a-h) x18: a,b x36: a-d
DQ(a-h) BYTE WRITE REGISTERS
CLK
D
Q
CE CE2 CE2 D Q
2/4/8
36, or 18
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK
OUTPUT REGISTERS
CLK OE
DQa - DQd
D
Q
ZZ
POWER DOWN
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
165-PIN BGA
165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array
BOTTOM VIEW
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
3
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
165 PBGA PACKAGE PIN CONFIGURATION
1M X 36 (TOP VIEW)
1 A B C D E F G H J K L M N P R NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE 2 A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC A 3 CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 5 BWb BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 6 CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss A A1* A0* 7 BWE GW Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 8 ADSC OE Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa A A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2, CE2 Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor Address Status Controller Global Write Enable Synchronous Clock Synchronous Chip Select Symbol BWE OE ZZ MODE NC DQx DQPx VDD VDDQ
Vss
Pin Name Byte Write Enable Output Enable Power Sleep Mode Burst Sequence Selection No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply
Isolated Output Power Supply 3.3V/2.5V Ground
BWx (x=a,b,c,d) Synchronous Byte Write Controls
4
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
165 PBGA PACKAGE PIN CONFIGURATION
2M X 18 (TOP VIEW)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE 2 A A NC DQb DQb DQb DQb NC NC NC NC NC NC NC A 3 CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 5 NC BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 6 CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss A A1* A0* 7 BWE GW Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 8 ADSC OE Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC A A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2, CE2 BWx (x=a,b) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor Address Status Controller Global Write Enable Synchronous Clock Synchronous Chip Select Synchronous Byte Write Controls Symbol BWE OE ZZ MODE NC DQx DQPx VDD VDDQ
Vss
Pin Name Byte Write Enable Output Enable Power Sleep Mode Burst Sequence Selection No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply
Isolated Output Power Supply 3.3V/2.5V Ground
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
5
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
PIN CONFIGURATION 100-PIN TQFP
DQPc
DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC A VSS VDD A A A A A A A A A
A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa
1M x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Controller Address Status Synchronous Processor Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Vss ZZ DQa-DQd DQPa-DQPd GW MODE OE VDD VDDQ Synchronous Data Input/Output Parity Data Input/Output Synchronous Global Write Enable Burst Sequence Mode Selection Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable
A ADSC ADSP ADV BWa-BWd BWE
CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock
6
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
PIN CONFIGURATION 100-PIN TQFP
A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC
A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Controller Address Status Synchronous Processor Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Synchronous Clock Synchronous Data Input/Output DQPa-DQPb GW MODE OE VDD VDDQ Vss ZZ Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 Synchronous Global Write Enable Burst Sequence Mode Selection Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable
A ADSC ADSP ADV BWa-BWb BWE CLK DQa-DQb
CE, CE2, CE2 Synchronous Chip Enable
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
MODE A A A A A1 A0 NC A VSS VDD A A A A A A A A A
2M x 18
7
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
TRUTH TABLE(1-8) (3CE option)
OPERATION Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Snooze Mode, Power-Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L X L L L L L X X H H X H X X H H X H CE2 X X H X H X L L L L L X X X X X X X X X X X X CE2 X L X L X X H H H H H X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP ADSC X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H ADV WRITE X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L OE X X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H Q High-Z Q High-Z D D Q High-Z Q High-Z D D DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z
NOTE: 1. X means "Don't Care." H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa's and DQPa. BWb enables WRITEs to DQb's and DQPb. BWc enables WRITEs to DQc's and DQPc. BWd enables WRITEs to DQd's and DQPd. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
8
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
TRUTH TABLE(1-8) (1CE option)
NEXT CYCLE Deselected Read, Begin Burst Read, Begin Burst Write, Begin Burst Read, Begin Burst Read, Begin Burst Read, Continue Burst Read, Continue Burst Read, Continue Burst Read, Continue Burst Write, Continue Burst Write, Continue Burst Read, Suspend Burst Read, Suspend Burst Read, Suspend Burst Read, Suspend Burst Write, Suspend Burst Write, Suspend Burst ADDRESS CE None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L L L L X X H H X H X X H H X H ADSP X L L H H H H H X X H X H H X X H X ADSC L X X L L L H H H H H H H H H H H H ADV X X X X X X L L L L L L H H H H H H WRITE X X X L H H H H H H L L H H H H L L OE X L H X L H L H L H X X L H L H X X DQ High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
NOTE: 1. X means "Don't Care." H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa's and DQPa. BWb enables WRITEs to DQb's and DQPb. BWc enables WRITEs to DQc's and DQPc. BWd enables WRITEs to DQd's and DQPd. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
9
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TSTG PD IOUT VIN, VOUT VIN VDD Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs Voltage on VDD Supply Relative to Vss Value Unit -55 to +150 C 1.6 W 100 mA -0.5 to VDDQ + 0.5 V -0.5 to VDD + 0.5 V -0.5 to 4.6 V
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
10
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
OPERATING RANGE (IS61LPSXXXXX)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V + 5% 3.3V + 5% VDDQ 3.3V / 2.5V + 5% 3.3V / 2.5V + 5%
OPERATING RANGE (IS61VPSXXXXX)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 2.5V + 5% 2.5V + 5% VDDQ 2.5V + 5% 2.5V + 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Vss VIN VDD
(1)
Test Conditions IOH = -4.0 mA (3.3V) IOH = -1.0 mA (2.5V) IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V)
Min. 2.4 -- 2.0 -0.3 -5 -5
Max. -- 0.4 VDD + 0.3 0.8 5 5
2.5V Min. Max. 2.0 -- 1.7 -0.3 -5 -5 -- 0.4 VDD + 0.3 0.7 5 5
Unit V V V V A A
Output Leakage Current Vss VOUT VDDQ, OE = VIH
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-200 MAX x18 x36 450 475 450 475 390 150 150 -166 MAX x18 x36 400 450 400 mA 450 340 120 120 mA
Symbol Parameter ICC AC Operating Supply Current
Test Conditions Device Selected, OE = VIH, ZZ VIL, All Inputs 0.2V or VDD - 0.2V, Cycle Time tKC min. Device Deselected, VDD = Max., All Inputs VIL or VIH, ZZ VIL, f = Max. Device Deselected, VDD = Max., VIN VSS + 0.2V or VDD - 0.2V f=0
Temp. range Com. Ind. typ.(2) Com. Ind.
Unit
ISB
Standby Current TTL Input
150 150
120 120
ISBI
Standby Current CMOS Input
Com. Ind. typ.(2)
110 140 75
110 140
110 140 75
110 140
mA
Note: 1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits 100A maximum leakage current when tied to VSS + 0.2V or VDD - 0.2V. 2. Typical values are measured at Vcc = 3.3V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
11
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2
AC TEST LOADS
317
ZO = 50 Output
3.3V
50
OUTPUT 5 pF Including jig and scope
Figure 2
351
1.5V
Figure 1
12
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
2.5V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4
2.5 I/O OUTPUT LOAD EQUIVALENT
317
ZO = 50 Output
2.5V
50
OUTPUT 5 pF Including jig and scope
Figure 4
351
1.25V
Figure 3
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
13
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-200 Symbol fMAX tKC tKH tKL tKQ tKQX
(2) (2,3)
Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Read/Write Setup Time Chip Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down
Min. -- 5 2 2 -- 1.5 1 -- -- 0 0 -- 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 -- --
Max. 200 -- -- -- 3.1 -- -- 3.0 3.1 -- -- 3.0 -- -- -- -- -- -- -- -- -- -- -- -- 2 2
-166 Min. Max. -- 6 2.4 2.4 -- 1.5 1 -- -- 0 0 -- 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.3 0.5 0.5 0.5 0.5 -- -- 166 -- -- -- 3.5 -- -- 3.4 3.5 -- -- 3.4 -- -- -- -- -- -- -- -- -- -- -- -- 2 2
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc
tKQLZ tOEQ
tKQHZ(2,3) tOEQX tOELZ tAS tSS tWS tCES tAVS tDS tAH tSH tWH tCEH tAVH tDH tPDS tPUS
(2)
(2,3)
tOEHZ(2,3)
Note: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2.
14
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
READ/WRITE CYCLE TIMING
tKC
CLK
tSS tSH tKH tKL
ADSP is blocked by CE inactive
tSH
ADSP
tSS
ADSC initiate read
ADSC
tAVS tAVH
Suspend Burst
ADV
tAS tAH
Address
RD1
tWS tWH
RD2
RD3
GW
tWS tWH
BWE
BWx
tCES tCEH
CE Masks ADSP
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
tOEQ tOEHZ
OE
tOELZ tOEQX tKQX
DATAOUT
High-Z
tKQLZ tKQ
1a
2a
2b
2c
2d
tKQHZ
DATAIN
High-Z Pipelined Read Single Read Burst Read Unselected
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
15
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
WRITE CYCLE TIMING
tKC
CLK
tSS tSH tKH tKL
ADSP is blocked by CE inactive
ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV
tAS tAH tAVH
Address
WR1
tWS tWH
WR2
WR3
GW
tWS tWH
BWE
tWS tWH tWS tWH
BWx
tCES tCEH
WR1
WR2 CE Masks ADSP
WR3
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
OE High-Z
tDS tDH
DATAOUT
DATAIN
High-Z
1a
BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d
3a
Single Write
Burst Write
Write
Unselected
16
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current Temperature Com. Ind. Conditions ZZ Vih Min. -- -- -- 2 -- 0 Max. 60 90 2 -- 2 -- Unit mA cycle cycle cycle ns
SNOOZE MODE TIMING
CLK
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All Inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z Don't Care
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
17
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O) Commercial Range: 0C to +70C
Configuration 1Mx36 166 IS61LPS102436A-166TQ IS61LPS102436A-166TQL IS61LPS102436A-166B3 IS61LPS204818A-166TQ IS61LPS204818A-166TQL IS61LPS204818A-166B3 100 TQFP 100 TQFP, Lead-free 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA Frequency Order Part Number Package
2Mx18 166
Industrial Range: -40C to +85C
Configuration 1Mx36 166 IS61LPS102436A-166TQI IS61LPS102436A-166TQLI IS61LPS102436A-166B3I IS61LPS102436A-166B3LI IS61LPS204818A-166TQI IS61LPS204818A-166B3I 100 TQFP 100 TQFP, Lead-free 165 PBGA 165 PBGA, Lead-free 100 TQFP 165 PBGA Frequency Order Part Number Package
2Mx18 166
18
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
ORDERING INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0C to +70C
Configuration 1Mx36 166 IS61VPS102436A-166TQ IS61VPS102436A-166TQL IS61VPS102436A-166B3 2Mx18 166 IS61VPS204818A-166TQ IS61VPS204818A-166TQL IS61VPS204818A-166B3 100 TQFP 100 TQFP, Lead-free 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA Frequency Order Part Number Package
Industrial Range: -40C to +85C
Configuration 2Mx18 166 IS61VPS204818A-166TQI IS61VPS204818A-166B3I 100 TQFP 165 PBGA Frequency Order Part Number Package
Integrated Silicon Solution, Inc.
Rev. B 03/27/08
19
PACKAGING INFORMATION
Ball Grid Array Package Code: B (165-pin)
TOP VIEW
A1 CORNER 1
A B C D E F G H J K L M N P R
b (165X)
BOTTOM VIEW
A1 CORNER 9 8 7 6 5 4 3 2 1
A B C D
2
3
4
5
6
7
8
9
10
11
11 10
e
E F G
D D1
H J K L M N P R
e E1 E A2 A1 A
BGA - 13mm x 15mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.25 -- 14.90 13.90 12.90 9.90 -- 0.40
INCHES Min. Nom. Max.
165
Notes: 1. Controlling dimensions are in millimeters.
Min.
Nom. Max.
165 -- 0.33 0.79 15.00 14.00 13.00 10.00 1.20 0.40 -- 15.10 14.10 13.10 10.10 -- 0.50
-- 0.010 -- 0.587 0.547 0.508 0.390 -- 0.016
-- 0.031 0.591 0.551 0.512 0.394 0.039 0.018
0.047 -- 0.594 0.555 0.516 0.398 -- 0.020
0.013 0.016
1.00
0.45
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 06/11/03
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package) Package Code: TQ
D D1
E
E1
N
1
C e SEATING PLANE
L1 L
A2 A1 b
A
Symbol Ref. Std. No. Leads (N) 100 A -- 1.60 -- 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. o o C 0 7 0o 7o
Millimeters Min Max
Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 -- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o
Inches Min Max
-- 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o
Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PK13197LQ Rev. D 05/08/03

▲Up To Search▲

Price & Availability of IS61VPS102436A

	To Download IS61VPS102436A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .